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Fall Processor Forum 2004 Wrap-Up
By Nick Stam


We trust you’ve read all of Mark Hachman’s excellent news reports located in our Fall Processor Forum main page. Mark provided insights on the upcoming AMD dual-core Opteron, Transmeta’s just-released TM8800 (aka “Efficeon 2”), and VIA/Centaur’s 64-bit-capable “CM” processor due in early 2006, along with various embedded processor news. In this wrap-up report, we’ll discuss the overarching themes at the show, review a fascinating technology keynote speech from IBM’s brilliant chief chip technologist Dr. Bernard Meyerson, highlight some very cool embedded processors announced at the show, and dig a bit deeper into the upcoming dual-core AMD Opteron.

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Before we get started, let’s clear up any possible confusion regarding the origins of the Fall Processor Forum. You may recall the old “Microprocessor Forum” held every October for the past 16 years. Show operator In-Stat/MDR decided to combine Microprocessor Forum with its Embedded Processor Forum, broadening the scope of the show, and running the event semiannually. Thus we’ll now see a “Fall Processor Forum” and “Spring Processor Forum” on an ongoing basis. Moderated by Microprocessor Report analysts, and including presentations from numerous microprocessor architects, the Forums are clearly great venues for learning details of future microprocessor architectures along with market positioning. While other shows such as ISSCC or Hot Chips might deliver more technical depth, Processor Forum strikes a good balance between technology insight and market factors.

The show included technical presentations of many upcoming embedded and server processors, and even a few chips used in supercomputer applications, but there weren’t many new mainstream processors (likely a major reason the show was more lightly attended than in the past), and Intel again skipped presenting at the show (see below).

The common architectural theme in nearly all presentations was a move away from building complicated, higher megahertz single core processors, to embedding multiple existing cores on a single die. Over the past few months, AMD, Intel and others have disclosed future “dual-core” designs for server, workstation, and even mainstream desktop and mobile processors. Other key design trends included system-on-a-chip (SoC) architectures for embedded applications, and more aggressively managed power utilization for processor cores.

Why the move to dual/multi-core? Because it’s getting increasingly difficult to build ever more complex, out-of-order processors that squeeze more parallelism out of an instruction stream (though certain processor architectures might do a better job than others, and/or work more closely with compilers to expose more parallelism). Equally important, it’s hard to scale clock frequencies into the stratosphere, because power requirements become unwieldy, and generated heat becomes extremely difficult to dissipate. A more readily attainable way to higher performance for many application scenarios is to include multiple lower-clocked cores on a single die.

You probably recall Intel cancelled the Prescott follow-on processor codenamed Tejas, and the Xeon (Nocona) follow-on codenamed Jayhawk, because of the “thermal wall” encountered at high GHz levels (beyond 4GHz) in the 90nm fabrication process, according to Intel President Paul Otellini earlier this year. In fact, moving to dual-core designs over the next year was an abrupt “right-turn” in Intel’s roadmap per Otellini.

Dual-core, quad-core, and even higher numbers of processor cores embedded on specialized chips will provide significant performance boosts for multithreaded applications and multiprocessing scenarios. Many server workloads and certain multithreaded and multiprocessing workstation applications will reap immediate benefits from multiple cores. A whole bunch of multimedia and imaging applications running in a variety of devices will benefit from multi-core embedded processors and DSP designs, as will network switches.

Back to Intel: Unfortunately, the company’s been notably absent the past few years at the (Micro)Processor Forum, with the excuse that its own developer forums are held too close in time to the Processor Forum, and there’s nothing much new to present. This may be true to a certain extent, but there’s always new stuff, and one could speculate that Intel is uncomfortable disclosing upcoming processor details to a roomful of highly technical competitors, especially with all its product delivery hiccups over the past few years. We wish Intel would reconsider for the Spring Processor Forum, but we won’t get our hopes up.

In the following pages we’ll take a look at some of the show highlights, starting with the excellent keynote.

     
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  • table of contents
    Introduction
    Driving System Performance—A New Paradigm
    Driving System Performance—A New Paradigm, continued
    Cool Technologies—Broadcom and MIPS
    Cool Technologies—Cavium, IBM, and TI
    AMD’s Dual-Core Opteron
    The Testy Benchmark Panel…


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